Engineered atomic interface enables ultra-thin gate dielectrics for 2D transistors

Researchers at National Yang Ming Chiao Tung University and TSMC Corporate Research have created a sub-nanometer interface that lets atomically thin transistors keep high performance while using extremely thin insulating layers.

A collaboration between National Yang Ming Chiao Tung University and TSMC Corporate Research has demonstrated that tailoring the atomic interface between a two-dimensional semiconductor and its gate dielectric can overcome a long-standing trade-off in ultra-thin transistors. By depositing an epitaxial aluminum film on monolayer MoS₂ and oxidizing it to form a 0.42-nanometer aluminum oxide layer, the researchers created a continuous buffer that both smooths the surface for a high-κ hafnium-oxide dielectric and prevents detrimental electrical interactions.

Devices built with this structure exhibited an equivalent oxide thickness near one nanometer, low leakage currents, negligible hysteresis, and a peak transconductance of 0.45 mS µm⁻¹ for 100-nanometer channels. The approach delivers the rare combination of aggressive dielectric scaling, robust gate control, and preserved carrier mobility, and it was achieved using CVD-grown material, suggesting compatibility with large-scale production. The findings highlight the growing importance of atomic-scale interface engineering as transistor dimensions approach the size of individual atoms, offering a new pathway beyond silicon’s limits.