Researchers unveil fast, low-error entangling gate for dual-rail erasure qubits

A new controlled-Z gate for superconducting dual-rail cavity qubits has been demonstrated, achieving about 500 ns operation time with erasure errors near 0.5% and Pauli errors below 0.1%. The gate preserves the favorable error hierarchy of erasure qubits, enabling more efficient quantum error correction.

Scientists have built a fast, high-fidelity two-qubit entangling operation for superconducting dual-rail cavity qubits, termed a ‘Swap-Wait-Swap’ (SWS) controlled-Z gate. By swapping an excitation from one cavity into a transmon coupler and allowing a calibrated dispersive interaction with the target cavity, the gate completes in about 500 ns while keeping erasure errors around 0.5% and residual Pauli errors below 0.1%.

Bit-flip errors are suppressed to the 10⁻⁶ level, and the control qubit exhibits higher erasure and dephasing rates due to the coupler’s lower coherence, a predictable asymmetry. Extensive benchmarking—including Bell-state tomography, interleaved randomized benchmarking, and repeated gate sequences—confirms these figures and reveals a strong bias toward dephasing over bit-flips. The authors also demonstrate that leakage during the gate translates into a benign conditional-dephasing error, allowing erasure checks to be delayed without harming surface-code thresholds. Numerical simulations suggest the structured noise can improve logical error suppression by a factor of roughly 10-20 as code distance grows, offering a viable path toward fault-tolerant quantum processors.