Huawei turns to stacked-chip design to bypass US EUV restrictions

American export controls have prevented Huawei from acquiring the extreme-ultraviolet lithography tools required for traditional transistor scaling, prompting the firm to explore a novel solution. At an IEEE conference in Shanghai, Huawei’s semiconductor head He Tingbo introduced LogicFolding, a chip architecture that folds a die in half and bonds two active layers face-to-face, effectively shortening wiring between transistors.

Huawei claims the approach can deliver a 55 % increase in transistor density and a 41 % improvement in power efficiency without shrinking the transistors themselves. The stacked design raises serious engineering hurdles, including thermal management, compounded yield losses on SMIC’s 5 nm-class process, and the need for new electronic-design-automation tools that remain immature. The first product employing LogicFolding, the Kirin 9050, will be integrated into the Mate 90 smartphone later this year, while Huawei targets its Ascend 990 AI accelerator for a 2030 rollout. Success will hinge on better SMIC yields, Chinese 3-D packaging licensing, and the emergence of production-grade EDA software.