SK hynix unveils new memory technologies to ease AI data bottlenecks

During a keynote at SEDEX 2026 in Seoul, SK hynix outlined a strategy to tackle growing AI inference bottlenecks by expanding beyond high-bandwidth memory (HBM). President and chief development officer Ahn Hyun warned that AI infrastructure performance requirements may increase about 19 times by 2030, shifting the challenge from processor-memory gaps to data movement across multiple memory layers. The firm will continue customizing HBM while also developing 3D-stacked DRAM that sits directly atop processors and high-bandwidth flash (HBF), which leverages HBM-style stacking to deliver roughly tenfold capacity at half the bandwidth.

HBF is positioned for workloads that read large data sets with few writes. SK hynix also plans to advance Compute Express Link and new storage technologies to streamline data transfer, and it emphasized the need for industry standards and partner cooperation. The exhibition featured an Nvidia Vera Rubin superchip and an HBM wafer signed by Nvidia CEO Jensen Huang, underscoring the partnership between the two companies.